1. Field of the Invention
The present invention relates to the field of memory testing. Specifically, an embodiment of the present invention relates to a test structure to measure interlayer dielectric charging and breakdown and detect metal defects in flash memories.
2. Related Art
The development of flash memory technology has resulted in re-writable memories that can hold its data content without power. As their technology has progressed, the density of flash memory devices increased. Correspondingly, backend processes involved in their production have become more complicated and more metal layers have become necessary to implement their functionality. Currently, a 3-level metal process constitutes the state of the art. However, in the foreseeable future, a 4-level or higher metal process will become necessary.
As more metal layers are added to advanced flash memory technology devices, the device densities increase and the layering and routing of the metal layers becomes complicated. Important characteristic properties of the flash memories must be maintained, notwithstanding the increasing densities and complication. These important characteristic flash memory properties include a high degree of data retention, a low degree of capacitive charge leakage, and a high degree reliability.
State of the art flash memories can reliably effectuate several hundred thousand program/erase cycles. Programming and erasing of flash memories is effectuated by relatively high program/erase voltages applied via metal lines. Applying the high voltage program/erase voltages via metal lines further challenges the backend process around the metal formation. One important such backend process is the formation of an interlayer dielectric (ILD) such as tetraethoxysilane (TEOS) between different layers of conductors. The conductors can include aluminum (Al), polycrystalline silicon (POLY), tungsten silicide (WSi2), and tungsten (W), among others.
Charge stability is crucial to the performance of flash memories, as compared to the performance of, for example regular logic devices. One difference between flash memories and regular logic devices is the operating voltages present. Regular logic devices typically operate with voltages on the order of 1.5 Volts. Flash memories, on the other hand, typically operate at higher voltages. Flash memory programming voltages can range from 5-7 Volts. Their erase voltages are even higher, ranging from 11-18 Volts. This is because, to effectuate the erase action, the voltage must be high enough to force electrons stored in a charged layer of the memory to tunnel through an tunnel oxide layer into substrate.
Designed for repeated cyclic operations at such high voltages, flash memory ILDs are subject to voltage driven stresses, which the ILDs of other devices, such as logic circuits, do not confront These voltage driven stresses may degrade the operating characteristics of the flash memory ILDs in several ways. Degradation of the dielectric integrity of the ILD is one such problem. Degradation of the ILD occurs when voltage stresses actually accumulate to damage the ILD in such a way that it no longer performs its dielectric function effectively.
When dielectric degradation occurs, the dielectric constant of the ILD is reduced. If dielectric degradation is severe enough, the dielectric can be punctured or burned through, allowing a conductive path through the ILD and effectively electrically shorting conductors meant to be insulated.
Charging of the ILD is another problem by which the operating characteristics of an flash memory ILD may be degraded. Charging effects are directly proportional to the voltages driving them. Thus, charging voltages in flash memories can be more problematic than in regular logic devices. Charging effects within the ILD can strongly effect charge stability, which is crucial to data storage within the flash memory in which the ILD is deployed. Thus, the dielectric properties of the ILD used in a flash memory device become critical to their performance.
Conventionally, dielectric integrity is tested by measuring the leakage current as a function of voltage and/or at a specific elevated voltage as a function of time for a flash memory device and its peripherals. ILD charging effects are conventionally determined by examining the threshold voltage (Vt) shifts of the flash memory and peripheral devices. However, these do not provide very accurate measurement of the properties of the ILD, itself. Rather, they test the overall dielectric integrity and charging effects of the entire flash memory and peripherals.
Considering charging effects for example, Vt is proportional to the charge QILD within the ILD. However, it is also proportional to the charge Q within the flash memory device, itself, as a total, complete assembly. Thus conventional Vt shift measurement can provide no information about the charging within the ILD itself that is not obfuscated by the effects of the other device and peripheral components. Determination of the dielectric integrity by the conventional means similarly obscures the dielectric integrity of the ILD itself. No conventional means exists to examine the dielectric integrity and/or the charging of the ILD used to fabricate a flash memory device, in and of itself.
Another backend process challenge particular to flash memories and related to the high voltage program/erase cycles involves the conductors, specifically the metal lines, in conjunction with the ILD. These metal lines constitute the wordlines and bitlines of the flash memories and ILD insulates them from each other and from other components of the flash memory device. Metal lines within flash memories are thin; they have thicknesses on the order of 4,000 Angstroms (xc3x85). However they are often quite long relative to their width; lengths on the order of several hundred microns are not uncommon for flash memories"" conductors.
Accordingly, the paths these conductors take through their insulating ILD matrix may be quite complex. These paths are often repeatedly articulated throughout the flash memory device, such that the metal conductors form corners. The current driven through these long, thin, articulated conductors by the voltages at which flash memories operate can cause problems in both the conductors themselves and the ILD insulating them. One such problem is local hot spots, which are portions of the conductor that rise in temperature relative to the rest of the conductor.
This heating is related in one instance to current crowding at the points of conductor articulation. This excess heat is dissipated into the surrounding ILD, and may cause defects such as voids or thermal transformations therein. These defects can reduce the dielectric constant of the ILD locally, and be reflected in overall dielectric degradation of the ILD as a whole. Further, voids can become so large that the ILD can fail as an insulator at the void, with concomitant electrical failures such as shorting.
Another problem related to the current driven through the conductors by the voltages at which flash memories operate is that of electromigration. Electromigration weakens the current carrying capabilities of the conductors by actual damage to the metal such as thinning and attendant local resistance increase and resulting production of even more heating in the area. The conductor can actually melt open, which causes electrical failure of the flash memory. Further, electromigration causes movement of metal atoms from the conductor into the surrounding ILD. This metal contamination then lowers the dielectric constant of the ILD, and makes possible compounding the conductor related problems with problems in the dielectric.
Conventional means to test the metal conductors used in flash memories typically are applied to the metal itself, without it being routed through and insulated by dielectric. This approach is problematic because it lacks in situ authenticity. Such conductors in real flash memories are routed within a matrix of ILD, which effects the metal both electrically and thermally and thus effects the degradation of the metal under test.
Thus, conventional testing approaches to flash memories suffer an inability to isolate the ILD under examination and observe effects thereon apart from the flash memory itself and peripherals. Further, conventional testing approaches to flash memories suffer an inability to examine effects on metal conductors in situ. Moreover, conventional testing approaches to flash memories requires a multiplicity of separate test structures, one to measure dielectric degradation, another to measure charging, and yet another to examine metal conductors. This is inefficient and costly.
A test structure to measure interlayer dielectric effects and breakdown and detect metal defects in flash memories is disclosed. In one embodiment, an apparatus for testing a dielectric property of a material constituting the interlayer dielectric of a flash memory device is formed by a layer of the dielectric material disposed throughout a test structure representative of the flash memory device and a plurality of conductors disposed within that layer, wherein the conductors function to electrically test the layer. A pair of planar conductors deposited such that the conductors are substantially parallel to each other and the layer of dielectric material is disposed throughout the test structure so as to separate the conductors such that the test structure functions as a capacitor. The apparatus may also test a conductive property of a material comprising the conducting lines of a flash memory device by disposing a conductor through the dielectric material.